FIG. 1 illustrates a prior art diagram of a Universal Serial Bus (USB) Specification Revision 2.0 (Apr. 27, 2000) (hereinafter USB2) system 100. System 100 has a host device 120 and a bus-powered device 150 connected to host device 120 by a USB2 cable 110. Host device 120 has a system board 122 and has on system board 122 an integrated circuit 124 having a USB2 host controller 130. USB2 host controller 130 has a transceiver circuit 132 to transmit data signals to and receive data signals from device 150 over differential data signal lines D+ 111 and D− 112 of USB2 cable 110. Device 150 similarly has a transceiver circuit 152 to communicate with transceiver circuit 132 over data signal lines D+ 111 and D− 112. Transceiver circuits 132 and 152 communicate using data signals that vary in voltage between approximately 3.3 V and ground. Integrated circuit 124 may be part of an input/output (I/O) controller chipset.
Host device 120 also has on system board 122 a voltage regulator module (VRM) 126 to provide an approximately 5 Volt (V) supply signal over a power line VBUS 115 of USB2 cable 110 to power device 150. Device 150 has a voltage regulator 154 to receive the 5V supply signal and provide regulated voltage supply to transceiver 152.
FIG. 2 illustrates a prior art diagram of a segment of USB2 cable 110. As illustrated in FIG. 2, USB2 cable 110 has differential data signal lines D+ 111 and D− 112, power line VBUS 115, and a ground line GND 118 that run adjacent to one another.
In the event of a short circuit of data signal line D+ 111 and/or D− 112 to power line VBUS 115, for example due to any crushing or cutting of a portion of USB2 cable 110, transceiver circuit 132, for example, would receive a 5V signal which is higher than the 3.3V data signal transceiver circuit 132 is designed to receive. Such a short circuit may therefore be potentially damaging to transceiver circuit 132. The Universal Serial Bus (USB) Specification Revision 2.0 (Apr. 27, 2000) (hereinafter USB2) states that a USB2 transceiver is required to withstand a continuous short circuit of data lines D+ and/or D− to the power bus VBUS for a minimum of twenty-four hours without degradation.
One mechanism to provide 5V protection in 3.3 V semiconductor fabrication technology is to stack transistors to avoid electrical overstress (EOS) damage if a 5V signal appears on data line D+ 111 and/or D− 112.
FIG. 3 illustrates a prior art diagram of circuitry for transceiver circuit 132 to protect transceiver circuit 132 from a 5V overvoltage condition on data line D+ 111 and/or D− 112. As illustrated in FIG. 3, transceiver circuit 132 includes a transmitter 310, a receiver 320, an overvoltage detector 330, and a programmable controller 340. Transmitter 310, receiver 320, and overvoltage detector 330 include circuitry as shown.
Transmitter 310 includes transistors to implement a high speed current source transmitter 312 and a complementary metal oxide semiconductor (CMOS) transmitter 314 to transmit data signals over data signal line D+ 111. As illustrated in FIG. 3, CMOS transmitter 314 has stacked transistors to avoid EOS damage if a 5V signal appears on data line D+ 111. Overvoltage detector 330 includes a voltage divider 332 and a differential amplifier 334 to detect whether a voltage in excess of 5V appears on data line D+ 111. Voltage divider 332 scales the voltage on data signal line D+ 111, and a differential amplifier 334 compares the scaled voltage to a reference voltage at node 333 having a value corresponding to a similarly scaled 5V signal. Differential amplifier 334 generates an overvoltage signal at node 335 if the scaled voltage exceeds the reference voltage. Programmable controller 340 sets transistor gate voltages to approximately those values shown in FIG. 3 in response to overvoltage signal at node 335 to avoid EOS damage.
This mechanism passively withstands the 5V signal on data line D+ 111. If the overvoltage is due to a short circuit of data signal line D+ 111 to power line VBUS 115 due to damage to USB2 cable 110, for example, the reliability of transceiver circuit 132 may nevertheless be at risk if the overvoltage condition is not addressed for a long period of time. Also, the feasibility of this mechanism is based at least in part on the voltage tolerance of the semiconductor fabrication technology. As semiconductor fabrication technology continues to scale, a transistor will be less able to withstand a higher voltage across its gate and diffusion. This mechanism will then not be able to meet the USB 2.0 Specification as the transistor will be more likely to degrade within twenty-four hours.
The figures of the drawings are not necessarily drawn to scale.